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Embedded Engines
Integrated High Performance Parsing and Classification Solution
High speed and high throughput packet error checking/detection, header parsing/extraction and packet classification are made simple by the PacketParser, Reconfigurable Arithmetic Unit (RAU) and Reconfigurable CAM (RCAM) CPE Blocks. These CPE blocks, along with the dataCrossconnect, provide designers with an integrated packet processing solution for 40 Gbps data rate and beyond.
HIGH PERFORMANCE PROGRAMMABLE AND SCALABLE PARSING SOLUTION
Create up to 32 Gbps of header parsing and extraction applications using each of the CS90 family’s embedded PacketParser CPE blocks. Using Cswitch’s productivity software, the Andara Development Tool Suite, designers can rapidly develop and program their applications into the PacketParser CPE blocks with the commonly used C programming language.
Custom Built Parser Engines
At the heart of each PacketParser is the custom built Parser Engine, a 16-bit programmable processor, running at speeds of up to 800MHz, and designed to analyze frame headers and extract fields efficiently. Each processor has dedicated instruction and data memory banks. The instruction memory holds 512 instructions of 21 bits each. The data memory has 256 bytes for application constants and two banks of 256 bytes each to hold a portion of a network packet.
Parallel Processing Maximized
The PacketParser CPE blocks also contain dedicated logic blocks and connections between multiple adjacent PacketParser CPE blocks to form a parser ring. When the parser ring structure is used, the built-in logic blocks split the incoming packets into a group of subpackets for processing called cells. The cells have user-configured size and are distributed in round-robin fashion to the PacketParsers CPE blocks of the ring.
Using the parser ring structure for a frame parsing application, a scalable highly parallel frame parsing system that never stalls can be created for continuous processing of streaming packets at a data rate of 40 Gbps and beyond.
The Andara Development Tool Suite – Productivity Software
The Andara Development Tool Suite, Cswitch’s comprehensive design software solution, includes the requisite tools to design the PacketParser application. The design entry is a custom application written in C. The Andara Development Tool Suite provides software to convert the C code into assembly code which is then loaded into the Parser Engine.  The Parser Engine computes the results, and can either send the result or prepend the result to the outgoing frame.
10G Ethernet Parsing Solution –
Scalable to 40 Gbps
An example application suited for the PacketParser CPE block, is a frame parser for 10G Ethernet. Parser rings of 7 PacketParser CPE blocks can implement a frame parser without stalling, even with minimum-size Ethernet packets of 64 bytes. This also assumes that the maximum path length through the code is 188 cycles. With up to 56 PacketParser CPE blocks, the largest CS90 family device can implement four copies of the Ethernet parser described above, for a total throughput of 40 Gbps.
Other applications of the PacketParser CPE block include, but are not limited to:
- Ethernet/IP/TCP parsing: Separate control frames from the data frames, extract information (e.g. 5-tuples), and identify boundaries.
- MPLS tagging and Martini encapsulation: Traverse the label stack, extract non-frame information from the Martini encapsulations, and identify the start of the encapsulated data.
- Fibre Channel: Separate FCP traffic from FC traffic and extract flow information.
INDUSTRY’S FIRST HIGH-PERFORMANCE RECONFIGURABLE EMBEDDED CAM
Design your high-speed packet classification applications using the built-in Reconfigurable CAM (RCAM) CPE Blocks. With a clock speed of up to 1GHz, the RCAM CPE Block is the fastest and the only embedded CAM available in a programmable logic device.
The RCAM CPE block can be configured to perform associative lookups as either a 64x40 binary CAM (BCAM), a 64x20 ternary CAM (TCAM), or a 64x32 bytewise CAM (ByteCAM), with an optional byte shifting logic for scanning of byte strings.
The RCAM CPE block has fully maskable key support, as well as a built-in Priority Encoder logic block. Additional logic blocks for match vector inversion, masking, and reversal before priority encoding are also included.
Dedicated connections allow the RCAM CPE blocks to be cascaded should deeper or wider CAM functions be needed. The RCAM CPE blocks can be cascaded into a chain of up to 32 RCAM CPE blocks, from up to 64 available blocks in the select CS90 family device. Should your system require additional embedded memories, the RCAM CPE block can be configured into a 64x40 single port SRAM.
RCAM CPE block applications include, but are not limited to:
- IP filters for firewalls in IPv4 and IPv6
- Multi Protocol Label Switching (MPLS) label class of service at gigabit rates
- VLAN Stacking (Q-in-Q)
INDUSTRY’S ONLY NETWORKING MATH ORIENTED ENGINE
 The Cswitch CS90 configurable switch array (CSA) contains up to 56 of the patented Reconfigurable Arithmetic Unit (RAU), running at speeds of up to 1GHz. The RAU is a highly configurable building block that can be used for complex arithmetic and logic functions. It is particularly adept at performing mathematics in Galois Fields (GF) which makes it keenly suited, but not limited, to computations commonly seen in networking and data storage devices. Applications such as CRC, encryption, transforms and filters can be implemented quickly and efficiently thanks to Cswitch’s library of RAU powered designs.
The RAU consists of an arithmetic fabric and accompanying tightly coupled logic. The arithmetic fabric is used to perform arithmetic functions such as addition and multiplication or logic functions such as Exclusive-Or (XOR). The arithmetic functions can be completed in a Galois Field, allowing for rapid calculations of CRCs, substitution box look-ups or Galois Field multiplicative inverses. The logic accompanying the arithmetic fabric includes registers and multiplexers, allowing for storage and selection of calculated results.
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