Connectivity

An Array of Choices for the Most Flexible Connectivity

The flexible CS90 Interface Tiles include I/O blocks that contain a variety of embedded, configurable I/O functions that include SERDES, MACs and source-synchronous data capture blocks. These built-in features allow designers to build any of the popular, networking-based, connection protocols between the CS90 family of devices and other external devices. The table below summarizes the supported I/O standards found in the CS90 family of devices:

The Quad MAC/PCS/SERDES (MPS) block provides four full-duplex channels of up to 6.4 Gbps serial transceivers for the CS90 family of devices. For transmitting data from the CS90 device, the transceiver contains a differential CML driver with up to 32 programmable swing levels, three-tap emphasis, 8 pre-cursor, and 8 post-cursor emphasis options. When receiving data into the CS90 device, the transceiver utilizes a differential CML receiver with equalization for enhanced jitter tolerance, clock and data recovery (CDR) circuitry, and programmable signal detection levels. Built-in AC coupling capacitors with multiple termination options are also provided.

Up to 40 full high speed serial transceivers, configurable to operate from 1.06 to 6.4 Gbps, are available in the CS90 family of devices. These transceivers work in conjunction with the built-in MAC and PCS layer logic blocks, and are compatible to popular standards such as 10/100/1000 Ethernet, Fibre Channel, and 10G Ethernet, for flexible implementation of high-speed serial protocols.

For more information on the MAC and PCS layer logic blocks please click on the following link (Link to the Networking Interface Page)

High-speed parallel interfaces for the CS90 family of devices are flexibly supported using single-ended and differential General Purpose I/Os (GPIOs).

The purpose of the GPIOs is to provide interfaces between CS90 and external devices through the built-in resources for analog and logic interfacing blocks at speeds of up to 1067 Mbps for select single-ended I/O standards, or up to 1000 Mbps for differential I/O standards.

Each GPIO contains programmable transmit and receive buffers, and supports multiple I/O standards. It also provides auto-calibrated drive impedance control, and on-die termination using an external reference resistor. The GPIO supports the following interfaces:

• LVDS (low-voltage signalling devices) at 2.5 V
• LDT (lightning data transport)
• 1.5V HSTL I, HSTL II, HSTL III
• SSTL I (1.8V, 2.5V), and SSTL II (1.8V, 2.5V)
• LVCMOS (low-voltage CMOS) at 1.5 V, 1.8 V, and 2.5 V
• GTLP
• Pseudo-differential I/O standards using a reference voltage

Each GPIO also contains built-in logic functions that provide the datapath between the user logic and the external interface. These functions improve system performance and conserve PLB resources. These functions include:

• Register and latches
• DDR-to-SDR and SDR-to-DDR conversion logic
• 16-deep FIFOs
• DLLs and per-bit delay lines that deskew source synchronous buses, providing adjustable timing on a pin-by-pin basis
• ECC logic that checks and corrects incoming data and encodes outgoing data
• Additional pipeline registers that can be configured as flip-flops or latches
• Phase adjustment

All GPIOs contain the analog and digital logic resources listed above. The GPIOs are all available for data interfacing because reference resistors and voltages are implemented using dedicated pins. Up to 640 GPIOs are available in the CS90 family of devices.

Links

• CS90 Datasheet (PDF, 4.3 MB)
• CS90 Overview (PDF, 808 KB)
• CS90 User Guide (PDF, 3.5 MB)
• GPIO Design Flow Guide (PDF, 273 KB)
• MPS User Guide (PDF, 3.1 MB)

BACK TO TOP